1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly relates to a semiconductor device of the ball grid array (hereinafter referred to as BGA) type and a method of forming the same.
In recent years, there has been a significant increase in circuit density of semiconductor devices, and, also, there has been an increasing demand for a higher density in implementing semiconductor devices. This leads to more attention being paid on semiconductor devices of the BGA type, which can make intervals of nodes wider than can those of the QFP type, and, also, can be implemented more closely to each other.
There has been also an increase in frequencies of signals processed by the semiconductor devices. Thus, semiconductor devices of the BGA type desirably have configurations which are suitable for the processing of high frequency signals
Also, the amount of heat generated by semiconductor chips has a tendency to increase as the semiconductor chips are made in higher circuit densities. Thus, semiconductor devices of the BGA type are required to have structures which are suitable for releasing heat.
2. Description of the Related Art.
FIG. 1 shows a semiconductor device of the BGA type disclosed in the U.S. Pat. No. 5,166,772.
A semiconductor device 10 includes an assembly board 11, a semiconductor chip 12 fixed to a central portion of an upper surface of the assembly board 11, solder balls 13 arranged at nodes of a grid pattern on a lower surface of the assembly board 11, and a cover 14 made of a resin for sealing the semiconductor chip 12.
In FIG. 1, wires 17 couple between pads 15 on the semiconductor chip 12 and pads 16 on the assembly board 11.
FIG. 2 shows an enlarged plan view of the assembly board 11 of FIG. 1. FIG. 3 shows a cross-sectional view of the assembly board 11 taken along a line shown as Axe2x80x94A in FIG. 2. As shown in FIG. 3, the assembly board 11 includes a printed board 20 and an additive layer 21 provided on the printed board 20. The assembly board 11 also includes through-holes 221 to 225.
Each of the pads 15 on the semiconductor chip 12 is electrically connected to a corresponding one of the solder balls 13 provided beneath the assembly board 11. For example, as can be seen in FIG. 1, FIG. 2, and FIG. 3, a pad 151 is connected to a solder ball 131 via a wire 171, a pad 161, a wiring pattern 23 on the additive layer 21, and a through-hole inner layer 24 provided on an inner surface of the through-hole 222.
In this configuration, the through-holes 221 to 225 are open holes, so that the additive layer 21 cannot be formed at the locations of the through-holes 221 to 225. Thus, wiring patterns on the additive layer 21 cannot be formed in such manner that they traverse the locations of the through-holes 221 to 225.
This leads to a restriction on formation of wiring patterns such that paths of the wiring patterns cannot be laid freely.
Take an example of forming a wiring pattern connecting the pad 151 and the through-hole 222. A straight wiring pattern 25 as shown by dotted lines in FIG. 2 cannot be formed. Thus, the wiring pattern 23 ends up having a bending shape detouring from a straight line in order to avoid the through-holes 221 and 225.
As a result, the wiring pattern 23 is bound to have a longer path length than otherwise. This is undesirable in terms of signal propagation, since signals having high frequencies may be distorted in the longer path.
Since the semiconductor chip 12 is sealed by the cover 14, it is difficult for heat generated by the semiconductor chip 12 to be transferred to the outside. Namely, the semiconductor device 10 is not suitably structured in terms of releasing heat.
Accordingly, there is a need in the field of semiconductor devices for a semiconductor device in which there is no restriction on formation of wiring paths and heat can be released with ease, and for a method of forming that semiconductor device.
Also, there is a need for a semiconductor device in which there is a wider scope for an arrangement of wirings for external connection.
Accordingly, it is a general object of the present invention to provide a semiconductor device and method of forming the same which satisfies the need described above.
It is another and more specific object of the present invention to provide a semiconductor device in which there is no restriction on formation of wiring paths and heat can be released with ease.
In order to achieve the above objects, a semiconductor device according to the present invention includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core, wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
Thus, according to the present invention, the through-holes are filled with the filling core, so that a single flat surface can be obtained, which is flush with the upper surface of the board base. This leads to the additive layer being formed on portions of the through-holes. With the additive layer covering the entire surface, there is no need to get around the through-holes when laying a wiring pattern.
Also, in the semiconductor device described above, the semiconductor chip can be fixed with its face down on the upper surface of the additive layer by a bonding process. Then, the semiconductor device can include a dam member having a frame shape and adhered to the upper surface of the board so as to surround the semiconductor chip, and a metal plate adhered to a back surface of the semiconductor chip and to the dam member.
Thus, according to the present invention, the metal plate adhered to the back surface of the semiconductor chip can release the heat generated by the semiconductor chip.
It is yet another object of the present invention to provide a method of forming a semiconductor device in which there is no restriction on formation of wiring paths.
In order to achieve the above object, a method of forming a semiconductor device according to the present invention includes the steps of forming through-holes through a board base, forming through-hole inner layers inside the through-holes by plating metal and by etching the metal to leave the through-hole inner layers, filling the through-holes with a synthetic resin, forming an insulator layer on the board base and on the synthetic resin filling the through-holes, forming a wiring pattern on the insulator layer by plating conductive metal and by etching the conductive metal to leave the wiring pattern, fixing a semiconductor chip over the board base, and forming nodes beneath a lower surface of the board base.
Thus, in the semiconductor device formed by the method described above, the through-holes are filled with the synthetic resin, so that there is no need to get around the through-holes when laying the wiring pattern.
It is still another object of the present invention to provide a semiconductor device in which there is a wider scope for an arrangement of wirings for external connection.
In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor chip having first electrodes on one surface thereof and at least one second electrode on another surface thereof, a board having first wirings and second wirings for external connection, wherein the first wirings are connected to the first electrodes so that the semiconductor chip is mounted on the board, and a conductive member covering the semiconductor chip so as to electrically connect at least one second electrode with the second wirings.
Thus, in the semiconductor device described above, at least one second electrode can be electrically connected with the second wirings via the conductive member. Since the conductive member completely covers the semiconductor chip, the second wirings can be anywhere around the semiconductor chip to be electrically connected to the conductive member. Thus, there is a wider scope for the arrangement of the second wirings for the external connection.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.